If we take a look at the top half, we see that P3_P4_P5 feeds the gate of Q1. Q1 is on if its gate is low, which means during P0_P1_P2. This means the signal X1 is pulled high during P0_P1_P2.
What about Q2? It is pulled high if Q11 is on, which happens when the gate of Q11 is low, which is during P0_P1_P2. But there's that pesky Q13 in there which could modify the behavior at the gate of Q2. So let's take a look at the bottom half.
The P1_P4 signal is gated at Q22 by P0_P1_P2. It will only pass if P0_P1_P2 is low, or if P3_P4_P5 is high. So the other side of Q22 is essentially P3_P4_P5 AND P1_P4, which is just P4. This is the signal Y-, which gets inverted at Q6 to form P0_P1_P2_P3_P5 at output Y1.
Now, P4 gets inverted at the gate of Q24, and then push-pull buffered at Q23/Q19, and low-buffered again at Q5. So this is still P0_P1_P2_P3_P5 at output Y1. So far, so good.
So the gate of Q13 is what comes out of Q24, which is P0_P1_P2_P3_P5. Q13 will only be on if its gate is low, which means P4.
Now look at Q11 again. It is on only if its gate is low, which means P0_P1_P2. So the signal X+ is pulled high if Q11 is on (P0_P1_P2) and low if Q13 is on (P4). The rest of the time it appears to just be floating.
However! Because Q13 has intrinsic capacitance, it will not immediately stop conducting. It will probably keep its state until some other thing drains it. So we can probably say Q13 is on, pulling the signal X+ low, during P3_P4_P5.
From this, we can talk about Q2. Q2 is on if its gate is low, which only happens on P3_P4_P5. And from before, Q1 is on if its gate is low, which means during P0_P1_P2. So in the end, we definitely have Q1/Q2 being a push-pull buffer for P0_P1_P2.
So why Q13 and not just an active load? Maybe because that would require essentially duplicating the circuit below, which requires four transistors aside from the push/pull output. The top circuit only needs two transistors.
Okay, we have reasoned out what this circuit should do. The conclusion is that signal X1 is P0_P1_P2 and signal Y1 is P0_P1_P2_P3_P5 (or /P4).
Is it what it really does? I'm dealing with unfamiliar PMOS territory here, and that appeal to Q13 retaining its state through two clock periods fills me with unease. One step to take is to actually build this circuit and see what happens. But that will be another blog post.
In the meantime, there's the left half of the circuit to deal with. It is nearly the same thing: