Reverse-engineering the 1977 Unisonic 21 calculator/game (part 5)

Previously, I found some clock signals (X1, Y1, X2, Y2).

clock2_simplified_pulses.jpg

These signals get spread throughout the chip to control the timing of various bits and pieces. One piece they go to is labeled in the main patent as "7-Segment Decode Logic".

block-diagram.jpg

The decode block has three inputs (aside from the assumed clock inputs): accumulator, C flip/flop, zero-suppression logic. The accumulator has four bits, and the C flip/flop is described as being able to be set, reset, tested, or loaded from the carry output of the adder.

The decode logic is described in this way: "The 10 data or segment output signals are generated at the output of a holding flip-flop in the segment decode logic shown in the lower right-hand portion of Fig. 3. The holding flip-flop for segment signals can be loaded through 7 segment display logic driven by the accumulator, or by dedicated bits when special symbols are required. The holding flip-flop for segment signal SEGP is loaded from the C flip-flop."

"SEGP" is likely the dot in each 7-segment display. The description also talks about 10 signals, rather than 7 (or 8 including the dot). This is because in the description of the overall block diagram, there are "up to 10 data outputs with options for discrete or seven-segment decoding logic, designated SEG0 through SEG9".

So, I started by working my way backwards from a known segment pin on the chip. 

segment_driver_left.jpg
segment_sch_driver_left.png

Please note that in the actual chip, VSS is connected to ground and VDD is connected to -14.6v. Because this confuses me, I consider the lower voltage as ground, and the higher voltage as VDD. Essentially I raised all voltages by 14.6v and relabeled the power connections.

As an aside, I noted that the PPS-4 datasheet states that the PPS-4 uses negative logic: a logic 1 is the most negative voltage, while a logic 0 is the most positive voltage.

First, I labeled the pin "SEG_21" because it is pin 21. I don't know what order the segments are in, so I just labeled them according to their pin. There are four signals common to all segments: CE, CG, IN_A, and IN_B. I don't know what they do yet, so the names are a bit random. There is also one signal coming from what appears to be the actual decode logic. I labeled this signal IN_21C.

Driving the pin is a large open-drain FET inverter.

Q3's gate is permanently connected to ground, which means it is on all the time. It seems that whatever C1 is, it is connected to gate of the output FET. The signals CE and CG appear to manipulate the state of C1. For example, with CG and CE both low, that would charge up capacitor C1 to VDD. If CE were high, through, it would discharge C1.

Let's simulate that:

segment_sim_driver_left.jpg

The result is not expected. The first time CG goes low, we do expect the capacitor to discharge when CE is high. Then, CG goes high which turns M1 off. At that point, I wouldn't expect CE to have any effect. But it does, because of the unfortunate substrate connection of M1. The body diode of M1 immediately conducts when CE goes low.

Luckily, LTSpice has a four-terminal PMOS. Let's use that instead.

segment_sim_driver_left_4pmos.jpg

This makes much more sense. Now when CG is low, the capacitor charges or discharges based on CE. When CG is high, the capacitor keeps its state. And the state of C1 is what comes out of M3, which would be the segment pin.

I made C1 relatively large on purpose so I could see it charge and discharge. Making it smaller just makes it charge and discharge faster.

All together, it looks like this section of the circuit is some kind of memory. But there is a problem. Well, two problems. The only four-terminal PMOS I know of is the MIC94030/31/50/51. So if that goes out of production, this circuit becomes nonviable.

But the main problem is the gate of M3. It can be pulled down by other FETs. What happens then?

Well, certainly M3 will be forced on, so the output state at the pin will be high. But I'm more concerned with what happens to capacitor C1. If the gate of M3 is pulled low, capacitor C1 must charge up. Then, if the gate of M3 is released, capacitor C1 will maintain the output state.

segment_sim_driver_left_4pmos_pulse.jpg

While the gate of M3 is pulled low, you don't want to turn M1 on, because then if CE is high, you would short through M1 and M2. Hopefully that doesn't happen.

So in the end, we're left with some kind of latching output. We can set the output high by connecting the gate of M3 temporarily to ground. We can clear this state by setting CE high and then pulsing CG low. We can also set the state by setting CE low and then pulsing CG low.

Reverse-engineering the 1977 Unisonic 21 calculator/game (part 4.5)

Hooray! I threw together an LTSpice simulation of the clock circuit from part 4, and it does what I thought it did!

sim_clock2.jpg

"OUT", the upper trace, is the Y1 signal. I was particularly interested to find out what happens at the gate of M5 when M1 is off, which is when P012 is high:

sim_clock2_node.jpg

That's interesting! It does remain low when M1's gate is high (so M1 is off), although it does rise up a few hundred millivolts depending on whether P14 is high or low.

In any case, simulating small parts of the chip like this is useful. It also gives confidence that if I make a printed circuit board for the circuit, it should work, barring some unforeseen integration issues.

The progress map now. Note that the unmarked section in the middle right is just interconnections.

progress_clock_gen2.jpg

Reverse-engineering the 1977 Unisonic 21 calculator/game (part 4)

A while ago I stopped working on reverse engineering the Unisonic 21. I think I was toddling after a shiny balloon. Anyway, I was recently talking with one of the creators of the MOnSter 6502 [see also Evil Mad Scientist's blog post] who mentioned he was looking for another chip to dis-integrate. I thought the Unisonic 21 CPU would make a nice target! But it needs to be fully reverse-engineered first. So, here we go again.

When we last left our reluctant hero, we had just seen a complicated circuit whose purpose was to provide a lot of oomph to create a high-powered clock driver.

Here is the full circuit:

clock2_sch.jpg

It's pretty huge, but we already know that all that capacitor stuff in the middle of each section is just there to drive the transistors hard. Let's remove all that clutter, and also replace the other bootstrap loads with plain old resistors and see what we're left with.

clock2_simplified_sch.jpg

OK, it's still a little cluttered. First, notice at the top that I've renamed the incoming clock signals according to the phases they are active in. This might help later.

Notice that Q16 is immediately recognizable as an inverter. That means the signal coming out of it is just P0_P1_P2: the other three of the six clock phases.

Now let's split the circuit down the middle and analyze the right half:

clock2_simplified_right_sch.jpg

If we take a look at the top half, we see that P3_P4_P5 feeds the gate of Q1. Q1 is on if its gate is low, which means during P0_P1_P2. This means the signal X1 is pulled high during P0_P1_P2.

What about Q2? It is pulled high if Q11 is on, which happens when the gate of Q11 is low, which is during P0_P1_P2. But there's that pesky Q13 in there which could modify the behavior at the gate of Q2. So let's take a look at the bottom half.

The P1_P4 signal is gated at Q22 by P0_P1_P2. It will only pass if P0_P1_P2 is low, or if P3_P4_P5 is high. So the other side of Q22 is essentially P3_P4_P5 AND P1_P4, which is just P4. This is the signal Y-, which gets inverted at Q6 to form P0_P1_P2_P3_P5 at output Y1.

Now, P4 gets inverted at the gate of Q24, and then push-pull buffered at Q23/Q19, and low-buffered again at Q5. So this is still P0_P1_P2_P3_P5 at output Y1. So far, so good.

So the gate of Q13 is what comes out of Q24, which is P0_P1_P2_P3_P5. Q13 will only be on if its gate is low, which means P4.

Now look at Q11 again. It is on only if its gate is low, which means P0_P1_P2. So the signal X+ is pulled high if Q11 is on (P0_P1_P2) and low if Q13 is on (P4). The rest of the time it appears to just be floating.

However! Because Q13 has intrinsic capacitance, it will not immediately stop conducting. It will probably keep its state until some other thing drains it. So we can probably say Q13 is on, pulling the signal X+ low, during P3_P4_P5.

From this, we can talk about Q2. Q2 is on if its gate is low, which only happens on P3_P4_P5. And from before, Q1 is on if its gate is low, which means during P0_P1_P2. So in the end, we definitely have Q1/Q2 being a push-pull buffer for P0_P1_P2.

So why Q13 and not just an active load? Maybe because that would require essentially duplicating the circuit below, which requires four transistors aside from the push/pull output. The top circuit only needs two transistors.

Okay, we have reasoned out what this circuit should do. The conclusion is that signal X1 is P0_P1_P2 and signal Y1 is P0_P1_P2_P3_P5 (or /P4).

Is it what it really does? I'm dealing with unfamiliar PMOS territory here, and that appeal to Q13 retaining its state through two clock periods fills me with unease. One step to take is to actually build this circuit and see what happens. But that will be another blog post.

In the meantime, there's the left half of the circuit to deal with. It is nearly the same thing:

clock2_simplified_left_sch.jpg

We can proceed in the same way, except we've already done most of this work. This circuit is identical to the right half, except that the signal feeding Q25's gate is P3_P4_P5 and the signal at X- is P0_P1_P2. But we will go through the exercise again. We start with the bottom half.

Q25 is on only if P1_P4 is high and if P3_P4_P5 is low (i.e. P0_P1_P2 is high). This means Q25 is on during P0_P1_P2 AND P1_P4, which is P1. This is signal Y-.

This is inverted by Q27, so Q27's output is /P1. Q30 is on only if /P1 is low, or during P1. And Q37 is on when Y- is low, which is during /P1, so Q30/Q37 is a push-pull buffer for /P1. This is signal Y+.

So, Q41/Q42 thus form a push-pull buffer for /P1. This is signal Y2. Note that signal Y1 was /P4.

Signal X- is low during P3_P4_P5, which pulls signal X2 high via Q44.

Q43 is on when signal X+ is low. This happens when Q29 is on, which happens when Q27 is off. This is during P1.

Q31, however, is on, pulling signal X+ high, when signal X- is low. This is during P3_P4_P5. Again, from the same reasoning, we can consider Q29 on, pulling X+ low during all other phases (especially P1 of course).

Q43 is on, pulling signal X2 low, when signal X+ is low, which is during P0_P1_P2. Q44 is on, pulling signal X2 high, when signal X- is low, which is during P3_P4_P5.

So we see that Q43/Q44 forms a push-pull buffer for P3_P4_P5. This is signal X2. Note that signal X1 was P0_P1_P2.

X1 is the opposite of X2, Y1 is a negative pulse in the middle of /X1, and Y2 is a negative pulse in the middle of /X2.

clock2_simplified_pulses.jpg

At least, this is what we hope it is. We'll just have to build the circuit and see.