Reverse-engineering the 1977 Unisonic 21 calculator/game (part 5.1)

Here's the next part of the segment driver circuit.


The output on the left goes to the latch-type output circuit from the previous post. On the right we have three inputs to this circuit. IN_A and X2 are common to all segments. IN_21C is an input specific to the segment at pin 21.

We can already guess that C3 is likely a bootstrap capacitor, so plays no logical role. It is also likely that C2 is a boosting capacitor for Q1. That means that X2 is the boosting signal.

Since C2 and C3 are boosting capacitors, we can ignore their effect in the steady state and concentrate on how the thing works logically.

X2 gates IN_21C at Q6. So the gate of Q5 is low only when Q6 is on and IN_21C is low.

Now, when Q5 is on, IN_A gets passed through to the gate of Q4. So when IN_A is low, that turns Q4 on, pulling the output low.

As we saw in part 5, pulling this output low will cause the output pin to latch high. The output can only go low when it is reset by that CE/CG combination.

So we've deduced that the output pin gets latched high only when IN_A goes low, IN_21C goes low, and X2 goes low.

Now, let's try simulating this. For this simulation, I am going to use the [MIC94030], because it is pretty much the only four-terminal PMOS left in existence, and I plan (hopefully) to use it for a dis-integrated version of the Unisonic 21.


It's a little busy, but I want to call your attention to a few things. First, I removed all the capacitors, and added pull-up resistors at all the gates.

Second, even though there is no existing SPICE model for this PMOS, I derived three parameters from the datasheet (Vt0 from the nominal threshold, and kp and lambda from the saturation graphs). So I have no idea if the simulation is accurate.

I've labeled successive gates in the circuit as nodes g1, g2, g3 and g4. Note that g1 goes low whenever IN_B and IN_21C are low, and that g2, g3, and g4 go low when all three inputs are low, as predicted. The output goes high when all three inputs are low.

What is important is the voltage at each gate when it is low. Going from g1 to g4, we appear to be losing a volt after every transistor. This is expected: without being boosted, you lose a threshold. This was explored in [the previous post about bootstraps].

It seems this loss of four volts is not enough to ruin the output of the last transistor which, after all, would have to have a gate voltage below 11v to turn on. Still, it would be nice to fix the issue. We can do that by adding bootstrap capacitors.

Think of bootstrap capacitors as adding feedback from the output back to the gate. If the output goes a little low, that just makes the gate go lower.

Here's one bootstrap capacitor. I set its capacitance so that you can just see the sag in the output.


We can see now that thanks to the bootstrap capacitor, g3 is able to reach a lower voltage than before. This gets translated to a lower voltage at g4. The capacitor, however, is not large enough to maintain its voltage over the period of the pulse.

Here I've increased the bootstrap capacitance from 1n to 10n:


Interestingly, adding a capacitor across the transistor M4 screws things up:


It seems that this capacitor is causing trouble. But adding one across M2 works fine, reducing the low voltage at g4 as expected:


I suspect bootstrap capacitors only work if one terminal of the transistor is grounded.

Anyway, this is another apparently successful simulation, meaning that it can probably be made physical.

Reverse-engineering the 1977 Unisonic 21 calculator/game (part 5)

Previously, I found some clock signals (X1, Y1, X2, Y2).


These signals get spread throughout the chip to control the timing of various bits and pieces. One piece they go to is labeled in the main patent as "7-Segment Decode Logic".


The decode block has three inputs (aside from the assumed clock inputs): accumulator, C flip/flop, zero-suppression logic. The accumulator has four bits, and the C flip/flop is described as being able to be set, reset, tested, or loaded from the carry output of the adder.

The decode logic is described in this way: "The 10 data or segment output signals are generated at the output of a holding flip-flop in the segment decode logic shown in the lower right-hand portion of Fig. 3. The holding flip-flop for segment signals can be loaded through 7 segment display logic driven by the accumulator, or by dedicated bits when special symbols are required. The holding flip-flop for segment signal SEGP is loaded from the C flip-flop."

"SEGP" is likely the dot in each 7-segment display. The description also talks about 10 signals, rather than 7 (or 8 including the dot). This is because in the description of the overall block diagram, there are "up to 10 data outputs with options for discrete or seven-segment decoding logic, designated SEG0 through SEG9".

So, I started by working my way backwards from a known segment pin on the chip. 


Please note that in the actual chip, VSS is connected to ground and VDD is connected to -14.6v. Because this confuses me, I consider the lower voltage as ground, and the higher voltage as VDD. Essentially I raised all voltages by 14.6v and relabeled the power connections.

As an aside, I noted that the PPS-4 datasheet states that the PPS-4 uses negative logic: a logic 1 is the most negative voltage, while a logic 0 is the most positive voltage.

First, I labeled the pin "SEG_21" because it is pin 21. I don't know what order the segments are in, so I just labeled them according to their pin. There are four signals common to all segments: CE, CG, IN_A, and IN_B. I don't know what they do yet, so the names are a bit random. There is also one signal coming from what appears to be the actual decode logic. I labeled this signal IN_21C.

Driving the pin is a large open-drain FET inverter.

Q3's gate is permanently connected to ground, which means it is on all the time. It seems that whatever C1 is, it is connected to gate of the output FET. The signals CE and CG appear to manipulate the state of C1. For example, with CG and CE both low, that would charge up capacitor C1 to VDD. If CE were high, through, it would discharge C1.

Let's simulate that:


The result is not expected. The first time CG goes low, we do expect the capacitor to discharge when CE is high. Then, CG goes high which turns M1 off. At that point, I wouldn't expect CE to have any effect. But it does, because of the unfortunate substrate connection of M1. The body diode of M1 immediately conducts when CE goes low.

Luckily, LTSpice has a four-terminal PMOS. Let's use that instead.


This makes much more sense. Now when CG is low, the capacitor charges or discharges based on CE. When CG is high, the capacitor keeps its state. And the state of C1 is what comes out of M3, which would be the segment pin.

I made C1 relatively large on purpose so I could see it charge and discharge. Making it smaller just makes it charge and discharge faster.

All together, it looks like this section of the circuit is some kind of memory. But there is a problem. Well, two problems. The only four-terminal PMOS I know of is the MIC94030/31/50/51. So if that goes out of production, this circuit becomes nonviable.

But the main problem is the gate of M3. It can be pulled down by other FETs. What happens then?

Well, certainly M3 will be forced on, so the output state at the pin will be high. But I'm more concerned with what happens to capacitor C1. If the gate of M3 is pulled low, capacitor C1 must charge up. Then, if the gate of M3 is released, capacitor C1 will maintain the output state.


While the gate of M3 is pulled low, you don't want to turn M1 on, because then if CE is high, you would short through M1 and M2. Hopefully that doesn't happen.

So in the end, we're left with some kind of latching output. We can set the output high by connecting the gate of M3 temporarily to ground. We can clear this state by setting CE high and then pulsing CG low. We can also set the state by setting CE low and then pulsing CG low.

Reverse-engineering the 1977 Unisonic 21 calculator/game (part 4.5)

Hooray! I threw together an LTSpice simulation of the clock circuit from part 4, and it does what I thought it did!


"OUT", the upper trace, is the Y1 signal. I was particularly interested to find out what happens at the gate of M5 when M1 is off, which is when P012 is high:


That's interesting! It does remain low when M1's gate is high (so M1 is off), although it does rise up a few hundred millivolts depending on whether P14 is high or low.

In any case, simulating small parts of the chip like this is useful. It also gives confidence that if I make a printed circuit board for the circuit, it should work, barring some unforeseen integration issues.

The progress map now. Note that the unmarked section in the middle right is just interconnections.