Rod Logic Memory

1. A 1-bit memory cell

Logic gates are great, but memory lets logic have state. My design for a 1-bit memory cell is somewhat different from Drexler's. In the diagram below, the green rod is the input rod, the blue rod is a state rod which stores the data, the left red rod is a latch rod, and the right red rod is the output rod.

1-bit memory

In order to store the value of the input rod, we first push the latch rod to the 1 position as shown above. Then we push the state rod two units to the right (if possible). Obviously if the input rod is 0, this can be done, but if the input rod is 1, it cannot:

Storing a 0, after pushing state rod

Finally, we reset the latch rod to 0, which has the effect of locking the state rod in place:

Storing a 0: reset the latch rod

Now we can see that if we try to read the memory cell by pushing the output rod, we cannot, which means the output is 0.

If, instead, the input rod had been 1, we would end up in the state shown here:

Storing a 1, after latch reset

Here we see that the output rod can be pushed, representing a 1 when the memory cell is read.

To erase the memory cell, we simply move the latch to 1, reset the state rod, and we are ready to store another value. Note that the output of an erased memory cell is 1. We could change that by moving the nub on the input rod down, so that the state rod is inhibited when the input is 0.  I started drawing the diagrams with the nub placed where shown, so I'll just leave it like that.

It's very important that when the memory cell is storing either a 0 or a 1, the input rod must be free to be reset, otherwise the logic attached to the input rod could not be reused after the value is stored in the memory cell. This is why the state rod is designed to move by two units.

2. A 4-bit register

There is still a slight problem with this design, which will be become apparent when we look at a 4-bit register based on this memory cell design:

4-bit memory

Here we have simply repeated the cell four times, keeping the latch rod common to all cells. This design works fine, as a little mental manipulation should show. However, there is one flaw which I don't like. Notice that all logic gate rods, and the input, state, and output rods in the memory cell are always spaced two units apart from each other. This regular grid makes it easy to connect gates to other gates. However, in a memory cell, the presence of the latch rod forces all the output rods to be off the regular grid by one unit. This would also require that special attention be paid to the housing of the rods where the latch is, and so a modular housing is not possible: holes for rods cannot be spaced two units apart, because the latch rod throws off the spacing.

There are two ways to solve this. The first involves moving the output rods to the right by three units, and moving the associated state nubs over by the same amount. If we only move the output rods one unit to the right, then the first (leftmost) output will not work:

4-bit memory, regular grid

Note that even though there is a space down the middle of the register, we can use that space for another rod for logic elsewhere, as long as that rod doesn't interfere in any way with the nubs on the state rods.

The second way is to move the output rods to another level, so that the state rods are sandwiched between the input and output rods. The latch rod remains on the same level as the input rods. This has the advantage of not taking up so much space along the state rod axis:

4-bit memory on three levels, input level

4-bit memory on three levels, output level

Once again, there is a required space in the register, this time on the left. Again, this space could be used by another rod for logic elsewhere, as long as the nubs on that rod do not interfere with the state rods.

3. 4x1 bit addressable memory

In this version of memory, we are able to read and write a single bit, but at four different locations specified by address rods. With the 4-bit register, we wrote four bits simultaneously by unlocking the four state rods, pushing them, and locking them again. We can use this same technique, but additionally condition the state rod movement on address rods (I corrected the input rod Din so that a reset state rod represents 0):

4x1 memory, input stage

Here, the top state rod is at address 00, the next at 01, the third at 10, and the bottom rod at 11. If and only if the address rods A0 and A1 are moved to the appropriate location can a state rod move.

Output is a little more difficult. We need to move a single rod based on the position of a particular state rod determined by address rods. Note that the address rods must be different, because they are for the output logic chain. If we reused the input address rods, then the input logic chain and output logic chain would not be independent. That is, we would not be able to reverse the input chain until the output chain were reversed, and so they would be part of the same chain.

Let us label the state rods S00, S01, S10, and S11. The output address rods will be O0 and O1, and the output rod will be X. I'll use - to indicate the not operation. And so, we have:

X = (-O0 -O1 S00) + (O0 -O1 S01) + (-O0 O1 S10) + (O0 O1 S11)

Each AND term can be implemented in one level of logic, while the final OR must be implemented in two levels. If, on the other hand, you don't mind negative logic, then the output rod could be -X instead of X, and then you don't have to implement the final inverter on the OR gate (i.e. it is now a NOR gate). This gives a memory output delay of two rather than three:

4x1 memory, output stage

The red intermediate rods implement the AND terms, while the green output rod implements the NOR term. The output rod could have been placed on the same level as the state and output address rods, but here I've decided to move it up a level.