First, corrections! It turns out that the things without the oxide layer that I thought were resistors were actually also capacitors. Also, there are PMOS transistors with thin, long gates that act as resistors. The gate is also connected to a constant voltage.
Finding which bond pad corresponded to which pin was a bit of a puzzle. The QIP package has 42 pins, of which only 31 are connected on the circuit board. The die, however, has 37 bond pads.
There is one round bond pad, and all the rest are square. The bond bad shown in the lower right of the image has a triangle attached to it. It is also electrically connected via the metal layer to another square bond pad also with a triangle.
The [patent] shows a block representing the chip connections to the PCB, and shows the connections in almost, but not quite, the same order as the pins on the chip.
It was enough order, though, and that, combined with tracing out the PCB and measuring signals, meant I was able to determine which pin was what. That allowed me to determine also which pin was which on the die. The round pin is, in fact, pin 1, not connected on the PCB. The square pin below it with the triangle is pin 42, which is VSS, which is also not connected on the PCB. It is electrically connected to pin 14, however, which is connected on the PCB, and does indeed go to ground.
Also helping were the fat output transistors for output pins. The ones without those transistors were clearly inputs such as PO, DIN1, and so on.
Bond pads that were missing were pins 3, 4, 12, 13, 16, none of which are connected on the PCB, except for pin 16 which is connected to ground.
With all pins identified, I could move on to looking for the block labeled "Osc and clock generator". This had pin VC going to it. I traced this out on the chip, and found the oscillator part to be three inverters connected in a ring, with an RC pair between each stage.
(See the [PDF version] on GitHub)
A few things that will look odd about this schematic. First, I label the positive voltage as +12v, and use the ground symbol for 0v. In fact, the actual circuit has the positive voltage (VDD) as 0v and the negative voltage (VSS) as -14.6v. Which really makes me crazy because everything is backwards from all of my circuit experience!
I also have a problem with telling drain from source. Luckily in these integrated circuits that differentiation is not present because with the body "terminal" connected to substrate, the MOSFET is a symmetrical device. There is no drain or source, only electrodes.
So anyway I just labelled VDD as positive and at the top, and VSS as ground and at the bottom. Also I set VDD to a familiar voltage.
Ignoring the timing, we have this diagram:
This results in a six-phase signal.
These signals feed into more logic which appears to be clock generating logic. I'll describe in the next post. But the interesting thing is that pin 2 is signal A!
I measured that signal and found it to have a high time (i.e. zero volts, which I'm calling logical 1) of 5.9 usec, and a low time (i.e. -14.6 volts, which I'm calling logical 0) of 6.6 usec for a total period of 12.5 usec (80 kHz).
Clearly all phases are not equal in time, because then the high time should be 6.25 usec and the low time also 6.25 usec. And this makes sense, given the different sizes of the resistors and capacitors in the inverter ring.
Further, I found a Rockwell patent filed in 1970, [US3641370], "Multiple-Phase Clock Signal Generator Using Frequency-Related and Phase-Separated Signals" showing a five-inverter version of this circuit. It also shows the VC signal (not by that name) controlling the resistances.
That patent, and also the 1966 patent [US3506851], "Field Effect Transistor Driver Using Capacitor Feedback" shows the pair of load transistors with the capacitor. The capacitor serves to drive the gate of the top transistor lower than the most negative voltage to really turn it on when it has to.
Thanks go to Ken Shirriff for pointing out that this circuit (which I traced but couldn't figure out) was likely a bootstrap load, also [used in the 4004 NMOS CPU] with the capacitor in a different location.
One minor aside: I tried to characterize the transistors by hooking up a resistor to pin 2 (the A signal) to get a current/voltage relationship.
By varying the resistance and measuring the voltage across it with my oscilloscope (not the most precision device), I could get an idea of what the current through the FET and the voltage across it were. By measuring several points, I could fit it to the MOSFET equation.
I validated that I was using the correct equation (linear or saturated) by checking those conditions were met. I knew W/L from looking at the die photo, in this case W/L was 12.
In the end, I came up with values of μpCox = 0.018 mA/V2, λ = 0.0527 V-1, and, oddly, Vsg - |VT| = 7.29 V which is almost exactly half the supply voltage. Since the "source" is also connected to the substrate, and is at +14.6v, and assuming that the gate is maximally driven at 0v, we see that VT would be -7.31 V, which seems a bit high to me. But it is still tempting to think that the engineers manipulated the doping to make the threshold exactly halfway between the two supplies.
Using these numbers, if I were to short the output to ground and calculate the current, it would be 10.2 mA. With Vsd of 14.6 V, that makes Rsd(on) 1.43 kΩ. Clearly not a MOSFET I'm used to, which has on resistances on the order of an ohm or less.
Anyway, I have no idea how realistic those numbers are.
In the next post, I'll show the next block, which seems to be clock phase generation logic.