Unisonic 21 single PMOS simulation in LTSpice

I used [LTSpice] to simulate the output circuit I previously measured and characterized.

Seems to work as expected. The primary assumption is that the gate is at ground. Honestly this doesn't prove a whole lot, just that the math behind best-fit worked. But it does serve as a base for more simulations, since I wanted to be sure I had the SPICE parameters correct for the PMOS.

Note that the substrate is connected to V1 rather than the "source" of the transistor. This will be true of all transistors in any simulation.

Here's a simulation of an inverter with a simple active load.

The output only rises to 12v because of the load of the output resistor in parallel with the resistance of the active load. I set the W/L of the upper transistor to 4/1 and the active load to 1/4, otherwise the upper transistor would not be strong enough to pull the output up away from the load transistor.

If we remove the output resistor entirely, we see that the active load cannot, in fact, drive the output to ground.

Here I will change the threshold from -7.3v to -1.5v. I really don't think the threshold is so large.

We see that the output is 1.5v when it should be 0v. It is, in fact, one threshold above ground.

Now, let's put together a bootstrap load circuit, as described in patent US3506851. First, without any capacitor. I have set M3 to 1/1.

As described in the patent, the output is off by two thresholds, at 3v. That's expected: you lose a threshold every time you add a transistor pulling to ground.

Now, let's add a capacitor. I've chose 0.01pF.

Look, the output went to ground! The reason is that when the output is high, the capacitor is charged up, and when the output voltage drops, the other end of the capacitor has to drop the same amount, since the capacitor does not want to change the voltage across itself.

This makes the gate on M3 go more negative, turning it on more strongly. Let's look at the gate voltage on M3.

See, it went very negative! It also slowly loses its charge because it will leak through the non-infinite resistance of M2.

Adding a load resistor to VPLUS makes the advantage even more stark:

The circuit without the bootstrap load is only capable of driving the output down to about 6.5v. The circuit with the bootstrap drives it below 1v.

The capacitor does have to be large enough that it doesn't leak all its charge away. Here's an example at 0.001pF.

By the way, this circuit doesn't work at all if the threshold goes back to -7.3v. That's why I think the threshold is wrong.

Anyway, that's the bootstrap load. It is used extensively in the CPU.