Tracing out the circuit section after the clock generator, I found some really large capacitors:
Next to each capacitor I've put their size in squares. C3 is familiar, being part of a bootstrap load. But what are huge capacitors C1 and C2 for? And why is there an extra capacitor C4 just hanging out across Q15?
Searching through the Rockwell patents, I found patent [US3480796], "MOS Transistor Driver Using a Control Signal". The reference at the beginning of the patent to a filing called "MOS Driver Using Capacitive Feedback" is, in fact, patent [US3506851] which I mentioned back in [part 2], and explored in the [bootstrap load simulation post].
In that simulation, we saw that the output voltage decayed, and it was worse with a really small capacitor in the bootstrap load. This patent is supposed to overcome that decay problem.
The input stage shown is an inverter. The original signal (8 in the diagram) drives the high-side transistor (5) while the inverted signal (4) drives the low-side transistor (1). There's an extra capacitor (C) and signal (17) which we need to explore. C1 in the diagram represents "the parasitic capacitance of the device", which for now I'll take to mean the gate capacitance of transistor 1.
I've redrawn this circuit, without the extra capacitor, in LTSpice. I've also flipped it so that the supply voltage is positive. Finally, the W/L of the transistors in the inverter are set as in the previous post, and the output transistors' W/L are set to 16/1 since they are supposed to be driver transistors.
Looking at G- (the red trace), we see that it goes from 1.5v to 14v as expected for a circuit without a bootstrap load. The output trace (blue) goes from 4.8v to 14.6v. That weak zero-level (4.8v) is due to the weak zero-level of the non-bootstrap load (1.5v). The weak zero-level is also what would happen if M9 were replaced with a bootstrap load with a very small capacitor, although there would be a brief period with a "good" output before the output decayed.
The patent describes adding a large capacitor at G-, fed by a signal Φ (VPH in the below schematic).
When the low-side transistor M1 is turned on (by G- going low, meaning IN is high), VPH goes high. This charges up the capacitor to VPLUS minus the threshold voltage (14.6-1.5, or 13.1v). Once the capacitor is charged up, VPH goes low, and because capacitors resist changes in voltage, this drives G- very negative, to -13.1v. And, like in the bootstrap load, this turns M1 on very strongly. The larger C1 is, the longer it will take for the output to decay.
In the simulation trace below, V(n001) is the PH signal. I've set it to be on for 0.1 msec.
We can see that after 0.1 msec, G- is driven very negative, which has the effect of turning M1 on strongly, which will let the output be driven strongly to 0v. We can also see that G- is decaying.
This circuit has the same effect as a bootstrap load, except that the capacitor is controlled by an external signal rather than the input signal. Why is this important?
For one, these output transistors are large and meant to drive heavy loads. Replacing the 100k output resistor with 10k barely changes the output voltage, but the bootstrap load cannot handle this output.
Also, large transistors come with large gate capacitances, which effectively adds more load.
So, that's the purpose of those large capacitors in the Unisonic 21 circuit. We can see that the signal marked PH is the external signal for capacitor C1 which helps drive Q2 low. Q9 and Q10 form a NAND gate. The /A signal is one input to that gate, while the other signal is an inverted delayed version of /A, courtesy Q14 and C4. The result is a pulse, which is just what is needed to drive the large capacitor.
What is also important is that for logical simulation purposes, this circuit has no effect. It is purely there to improve the drive characteristics of the output, and if the output is idealized, this circuit disappears.