Hooray! I threw together an LTSpice simulation of the clock circuit from part 4, and it does what I thought it did!
"OUT", the upper trace, is the Y1 signal. I was particularly interested to find out what happens at the gate of M5 when M1 is off, which is when P012 is high:
That's interesting! It does remain low when M1's gate is high (so M1 is off), although it does rise up a few hundred millivolts depending on whether P14 is high or low.
In any case, simulating small parts of the chip like this is useful. It also gives confidence that if I make a printed circuit board for the circuit, it should work, barring some unforeseen integration issues.
The progress map now. Note that the unmarked section in the middle right is just interconnections.