Here's the next part of the segment driver circuit.
The output on the left goes to the latch-type output circuit from the previous post. On the right we have three inputs to this circuit. IN_A and X2 are common to all segments. IN_21C is an input specific to the segment at pin 21.
We can already guess that C3 is likely a bootstrap capacitor, so plays no logical role. It is also likely that C2 is a boosting capacitor for Q1. That means that X2 is the boosting signal.
Since C2 and C3 are boosting capacitors, we can ignore their effect in the steady state and concentrate on how the thing works logically.
X2 gates IN_21C at Q6. So the gate of Q5 is low only when Q6 is on and IN_21C is low.
Now, when Q5 is on, IN_A gets passed through to the gate of Q4. So when IN_A is low, that turns Q4 on, pulling the output low.
As we saw in part 5, pulling this output low will cause the output pin to latch high. The output can only go low when it is reset by that CE/CG combination.
So we've deduced that the output pin gets latched high only when IN_A goes low, IN_21C goes low, and X2 goes low.
Now, let's try simulating this. For this simulation, I am going to use the [MIC94030], because it is pretty much the only four-terminal PMOS left in existence, and I plan (hopefully) to use it for a dis-integrated version of the Unisonic 21.
It's a little busy, but I want to call your attention to a few things. First, I removed all the capacitors, and added pull-up resistors at all the gates.
Second, even though there is no existing SPICE model for this PMOS, I derived three parameters from the datasheet (Vt0 from the nominal threshold, and kp and lambda from the saturation graphs). So I have no idea if the simulation is accurate.
I've labeled successive gates in the circuit as nodes g1, g2, g3 and g4. Note that g1 goes low whenever IN_B and IN_21C are low, and that g2, g3, and g4 go low when all three inputs are low, as predicted. The output goes high when all three inputs are low.
What is important is the voltage at each gate when it is low. Going from g1 to g4, we appear to be losing a volt after every transistor. This is expected: without being boosted, you lose a threshold. This was explored in [the previous post about bootstraps].
It seems this loss of four volts is not enough to ruin the output of the last transistor which, after all, would have to have a gate voltage below 11v to turn on. Still, it would be nice to fix the issue. We can do that by adding bootstrap capacitors.
Think of bootstrap capacitors as adding feedback from the output back to the gate. If the output goes a little low, that just makes the gate go lower.
Here's one bootstrap capacitor. I set its capacitance so that you can just see the sag in the output.
We can see now that thanks to the bootstrap capacitor, g3 is able to reach a lower voltage than before. This gets translated to a lower voltage at g4. The capacitor, however, is not large enough to maintain its voltage over the period of the pulse.
Here I've increased the bootstrap capacitance from 1n to 10n:
Interestingly, adding a capacitor across the transistor M4 screws things up:
It seems that this capacitor is causing trouble. But adding one across M2 works fine, reducing the low voltage at g4 as expected:
I suspect bootstrap capacitors only work if one terminal of the transistor is grounded.
Anyway, this is another apparently successful simulation, meaning that it can probably be made physical.