Reverse-engineering the 1977 Unisonic 21 calculator/game (part 5)

Previously, I found some clock signals (X1, Y1, X2, Y2).

clock2_simplified_pulses.jpg

These signals get spread throughout the chip to control the timing of various bits and pieces. One piece they go to is labeled in the main patent as "7-Segment Decode Logic".

block-diagram.jpg

The decode block has three inputs (aside from the assumed clock inputs): accumulator, C flip/flop, zero-suppression logic. The accumulator has four bits, and the C flip/flop is described as being able to be set, reset, tested, or loaded from the carry output of the adder.

The decode logic is described in this way: "The 10 data or segment output signals are generated at the output of a holding flip-flop in the segment decode logic shown in the lower right-hand portion of Fig. 3. The holding flip-flop for segment signals can be loaded through 7 segment display logic driven by the accumulator, or by dedicated bits when special symbols are required. The holding flip-flop for segment signal SEGP is loaded from the C flip-flop."

"SEGP" is likely the dot in each 7-segment display. The description also talks about 10 signals, rather than 7 (or 8 including the dot). This is because in the description of the overall block diagram, there are "up to 10 data outputs with options for discrete or seven-segment decoding logic, designated SEG0 through SEG9".

So, I started by working my way backwards from a known segment pin on the chip. 

segment_driver_left.jpg
segment_sch_driver_left.png

Please note that in the actual chip, VSS is connected to ground and VDD is connected to -14.6v. Because this confuses me, I consider the lower voltage as ground, and the higher voltage as VDD. Essentially I raised all voltages by 14.6v and relabeled the power connections.

As an aside, I noted that the PPS-4 datasheet states that the PPS-4 uses negative logic: a logic 1 is the most negative voltage, while a logic 0 is the most positive voltage.

First, I labeled the pin "SEG_21" because it is pin 21. I don't know what order the segments are in, so I just labeled them according to their pin. There are four signals common to all segments: CE, CG, IN_A, and IN_B. I don't know what they do yet, so the names are a bit random. There is also one signal coming from what appears to be the actual decode logic. I labeled this signal IN_21C.

Driving the pin is a large open-drain FET inverter.

Q3's gate is permanently connected to ground, which means it is on all the time. It seems that whatever C1 is, it is connected to gate of the output FET. The signals CE and CG appear to manipulate the state of C1. For example, with CG and CE both low, that would charge up capacitor C1 to VDD. If CE were high, through, it would discharge C1.

Let's simulate that:

segment_sim_driver_left.jpg

The result is not expected. The first time CG goes low, we do expect the capacitor to discharge when CE is high. Then, CG goes high which turns M1 off. At that point, I wouldn't expect CE to have any effect. But it does, because of the unfortunate substrate connection of M1. The body diode of M1 immediately conducts when CE goes low.

Luckily, LTSpice has a four-terminal PMOS. Let's use that instead.

segment_sim_driver_left_4pmos.jpg

This makes much more sense. Now when CG is low, the capacitor charges or discharges based on CE. When CG is high, the capacitor keeps its state. And the state of C1 is what comes out of M3, which would be the segment pin.

I made C1 relatively large on purpose so I could see it charge and discharge. Making it smaller just makes it charge and discharge faster.

All together, it looks like this section of the circuit is some kind of memory. But there is a problem. Well, two problems. The only four-terminal PMOS I know of is the MIC94030/31/50/51. So if that goes out of production, this circuit becomes nonviable.

But the main problem is the gate of M3. It can be pulled down by other FETs. What happens then?

Well, certainly M3 will be forced on, so the output state at the pin will be high. But I'm more concerned with what happens to capacitor C1. If the gate of M3 is pulled low, capacitor C1 must charge up. Then, if the gate of M3 is released, capacitor C1 will maintain the output state.

segment_sim_driver_left_4pmos_pulse.jpg

While the gate of M3 is pulled low, you don't want to turn M1 on, because then if CE is high, you would short through M1 and M2. Hopefully that doesn't happen.

So in the end, we're left with some kind of latching output. We can set the output high by connecting the gate of M3 temporarily to ground. We can clear this state by setting CE high and then pulsing CG low. We can also set the state by setting CE low and then pulsing CG low.